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products and specifications discussed herein are subject to change by micron without notice. 1 16 meg: x4, x8 sdram ?1998, micron technology, inc. 16msdramx4x8_b.p65 C rev. 5/98 16 meg: x4, x8 sdram 16mb (x4/x8) sdram part numbers part number architecture mt48lc4m4a1tg s 4 meg x 4 ( t wr = 1 clk) MT48LC2M8A1tg s 2 meg x 8 ( t wr = 1 clk) 4 meg x 4 2 meg x 8 configuration 2 meg x 4 x 2 banks 1 meg x 8 x 2 banks refresh count 4k 4k row addressing 2k (a0-a10) 2k (a0-a10) bank addressing 2 (ba) 1 (ba) column addressing 1k (a0-a9) 512 (a0-a8) features ? pc100-compliant; includes concurrent auto precharge ? fully synchronous; all signals registered on positive edge of system clock ? internal pipelined operation; column address can be changed every clock cycle ? internal banks for hiding row access/precharge ? programmable burst lengths: 1, 2, 4, 8, or full page ? auto precharge and auto refresh modes ? self refresh mode ? 64ms, 4,096-cycle refresh ? lvttl-compatible inputs and outputs ? single +3.3v 0.3v power supply ? longer lead tsop for improved reliability (ocpl*) ? one- and two-clock write recovery ( t wr) versions options marking ? configurations 4 meg x 4 (2 meg x 4 x 2 banks) 4m4 2 meg x 8 (1 meg x 8 x 2 banks) 2m8 ? write recovery ( t wr/ t dpl) t wr = 1 clk a1 t wr = 2 clk (contact factory for availability.)a2 ? plastic package - ocpl* 44-pin tsop (400 mil) tg ? timing (cycle time) 8ns; t ac = 6ns @ cl = 3 -8b 10ns; t ac = 9ns @ cl = 2 -10 note: the 16mb sdram base number differentiates the offerings in two places: mt48lc 2m8a1 s. the fourth field distinguishes the architecture offering: 4m4 designates 4 meg x 4, and 2m8 designates 2 meg x 8. the fifth field distinguishes the write recovery offering: a1 designates one clk and a2 designates two clks. part number example: MT48LC2M8A1tg-10 s pin assignment (top view) 44-pin tsop v dd dq0 vssq dq1 v dd q dq2 vssq dq3 v dd q nc nc we# cas# ras# cs# ba a10 a0 a1 a2 a3 v dd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 vss dq7 vssq dq6 v dd q dq5 vssq dq4 v dd q nc nc dqm clk cke nc a9 a8 a7 a6 a5 a4 vss - nc - dq0 - nc - dq1 - - - - - - - - - - - - - - - nc - dq3 - nc - dq2 - - - - - - - - - - - - - - x4 x8 x8 x4 note: the # symbol indicates signal is active low. a dash (-) indicates x4 pin function is same as x8 pin function. synchronous dram mt48lc4m4a1/a2 s - 2 meg x 4 x 2 banks MT48LC2M8A1/a2 s - 1 meg x 8 x 2 banks for the latest data sheet revisions, please refer to the micron web site: www.micron.com/datasheets . key timing parameters speed clock access time setup hold grade frequency cl = 2** cl = 3** time time -8b 125 mhz C 6ns 2ns 1ns -10 100 mhz C 7.5ns 3ns 1ns -8b 83 mhz 9ns C 2ns 1ns -10 66 mhz 9ns C 3ns 1ns * off-center parting line **cl = cas (read) latency
2 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram general description the micron 16mb sdram is a high-speed cmos, dynamic random-access memory containing 16,777,216 bits. it is internally configured as a dual memory array (the 4 meg x 4 is a dual 2 meg x 4, and the 2 meg x 8 is a dual 1 meg x 8) with a synchronous interface (all signals are registered on the positive edge of the clock signal, clk). each of the two internal banks is organized with 2,048 rows and either 1,024 columns by 4 bits (4 meg x 4) or 512 columns by 8 bits (2 meg x 8). read and write accesses to the sdram are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an ac- tive command, which is then followed by a read or write command. the address bits registered coinci- dent with the active command are used to select the bank and row to be accessed (ba selects the bank, a0-a10 select the row). the address bits registered coincident with the read or write command are used to select the starting column location for the burst access. the sdram provides for programmable read or write burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. an auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. the micron 16mb sdram uses an internal pipelined architecture to achieve high-speed operation. this ar- chitecture is compatible with the 2 n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a high-speed, fully random access. precharging one bank while access- ing the alternate bank will hide the precharge cycles and provide seamless, high-speed, random-access op- eration. the micron 16mb sdram is designed to operate in 3.3v, low-power memory systems. an auto refresh mode is provided, along with a power-saving, power-down mode. all inputs and outputs are lvttl-compatible. sdrams offer substantial advances in dram operat- ing performance, including the ability to synchronously burst data at a high data rate with automatic column- address generation, the ability to interleave between in- ternal banks in order to hide precharge time, and the capability to randomly change column addresses on each clock cycle during a burst access.
3 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram table of contents functional block diagram - 4 meg x 4 ........................ 4 functional block diagram - 2 meg x 8 ........................ 5 pin descriptions ............................................................ 6 functional description ................................................ 7 initialization ............................................................. 7 register definitions ................................................. 7 mode register ..................................................... 7 burst length .................................................. 7 burst type ..................................................... 7 cas latency .................................................. 9 operating mode ............................................ 9 write burst mode ......................................... 9 commands ..................................................................... 10 truth table 1 (commands and dqm operation) ....... 10 command inhibit .............................................. 11 no operation (nop) .......................................... 11 load mode register ........................................... 11 active ................................................................... 11 read ..................................................................... 11 write .................................................................... 11 precharge ............................................................ 11 auto precharge ................................................... 11 burst terminate ................................................. 11 auto refresh ....................................................... 12 self refresh ......................................................... 12 operation ....................................................................... 13 bank/row activation ......................................... 13 reads ................................................................... 14 writes .................................................................. 20 precharge ............................................................ 22 power-down ....................................................... 22 clock suspend .................................................... 23 burst read/single write .................................... 23 concurrent auto precharge .............................. 24 truth table 2 (cke) ................................................. 26 truth table 3 (current state) .................................... 27 truth table 4 (current state) .................................... 29 absolute maximum ratings ......................................... 31 dc electrical characteristics and operating conditions . 31 i cc operating conditions and maximum limits ........ 31 capacitance .................................................................... 32 ac electrical characteristics (timing table) ............ 32 timing waveforms initialize and load mode register ......................... 35 power-down mode .................................................. 36 clock suspend mode ............................................... 37 auto refresh mode .................................................. 38 self refresh mode .................................................... 39 reads read - without auto precharge ........................ 40 read - with auto precharge .............................. 41 alternating bank read accesses ....................... 42 read - full-page burst ....................................... 43 read - dqm operation ...................................... 44 writes write - without auto precharge ....................... 45 write - with auto precharge ............................. 46 alternating bank write accesses ...................... 47 write - full-page burst ...................................... 48 write - dqm operation ..................................... 49
4 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram functional block diagram 4 meg x 4 sdram 11 11 11 ras# refresh controller 2,048 refresh counter cas# 1,024 1,024 (x4) 10 column- address buffer burst counter row- address mux clk cs# we# cke 1,024 (x4) bank 1 memory array (2,048 x 1,024 x 4) sense amplifiers i/o gating dqm mask logic control logic column decoder column- address latch 10 mode register row- address latch 11 row decoder 11 command decode dq0 - dq3 a0-a10, ba 4 8 dqm 1,024 2,048 bank 0 memory array (2,048 x 1,024 x 4) row decoder row- address latch 11 12 address register 12 sense amplifiers i/o gating dqm mask logic data input register data output register 4 4
5 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram functional block diagram 2 meg x 8 sdram 11 11 11 ras# refresh controller 2,048 refresh counter cas# 512 512 (x8) 9 column- address buffer burst counter row- address mux clk cs# we# cke 512 (x8) bank 1 memory array (2,048 x 512 x 8) sense amplifiers i/o gating dqm mask logic control logic column decoder column- address latch 9 mode register row- address latch 11 row decoder 11 command decode dq0 - dq7 a0-a10, ba 8 8 dqm 512 2,048 bank 0 memory array (2,048 x 512 x 8) row decoder row- address latch 11 12 address register 12 sense amplifiers i/o gating dqm mask logic data input register data output register 8 8
6 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram pin descriptions pin numbers symbol type description 32 clk input clock: clk is driven by the system clock. all sdram input signals are sampled on the positive edge of clk. clk also increments the internal burst counter and controls the output registers. 31 cke input clock enable: cke activates (high) and deactivates (low) the clk signal. deactivating the clock provides precharge power-down and self refresh operations (all banks idle), active power-down (row active in either bank), or clock suspend operation (burst/access in progress). cke is synchronous except after the device enters power-down and self refresh modes, where cke becomes asynchronous until after exiting the same mode. the input buffers, including clk, are disabled during power-down and self refresh modes, providing low standby power. cke may be tied high. 15 cs# input chip select: cs# enables (registered low) and disables (registered high) the command decoder. all commands are masked when cs# is registered high. cs# provides for external bank selection on systems with multiple banks. cs# is considered part of the command code. 14, 13, ras#, cas#, input command inputs: ras#, cas#, and we# (along with cs#) define the command 12 we# being entered. 33 dqm input input/output mask: dqm is an input mask signal for write accesses and an output enable signal for read accesses. input data is masked when dqm is sampled high during a write cycle. the output buffers are placed in a high-z state (after a two-clock latency) when dqm is sampled high during a read cycle. 16 ba input bank address: ba defines to which bank the active, read, write, or precharge command is being applied. ba is also used to program the twelfth bit of the mode register. 18-21, 24-29, 17 a0-a10 input address inputs: a0-a10 are sampled during the active command (row-address a0-a10) and read/write command (column-address a0-a9 [x4]; a0-a8 [x8], with a9 as a dont care; and with a10 defining auto precharge) to select one location out of the memory array in the respective bank. a10 is sampled during a precharge command to determine if both banks are to be precharged (a10 high). the address inputs also provide the op-code during a load mode register command. 4, 8, 37, 41 x4: dq0, 1, 2, 3 input data i/o: data bus. x8: dq1, 3, 4, 6 2, 6, 39, 43 x4: nc C no connect: these pins should be left unconnected. x8: dq0, 2, 5, 7 input data i/o: data bus. 10, 11, 30, 34, 35 nc C no connect: these pins should be left unconnected. 5, 9, 36, 40 v dd q supply dq power. 3, 7, 38, 42 v ss q supply dq ground. 1, 22 v dd supply power supply: +3.3v 0.3v. 23, 44 v ss supply ground.
7 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram functional description in general, the sdram is a dual memory array (the 4 meg x 4 is a dual 2 meg x 4, and the 2 meg x 8 is a dual 1 meg x 8) which operates at 3.3v and includes a synchro- nous interface (all signals are registered on the positive edge of the clock signal, clk). each of the two internal banks is organized with 2,048 rows and either 1,024 col- umns by 4 bits (4 meg x 4) or 512 columns by 8 bits (2 meg x 8). read and write accesses to the sdram are burst ori- ented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of an ac- tive command, which is then followed by a read or write command. the address bits registered coinci- dent with the active command are used to select the bank and row to be accessed (ba selects the bank, a0-a10 select the row). the address bits (a0-a9; a9 is a dont care for x8) registered coincident with the read or write command are used to select the starting column location for the burst access. prior to normal operation, the sdram must be ini- tialized. the following sections provide detailed infor- mation covering device initialization, register definition, command descriptions and device operation. initialization sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined operation. once power is applied to v dd and v dd q (simultaneously) and the clock is stable, the sdram requires a 100s delay prior to applying an executable command. the ras#, cas#, we# and cs# inputs should be held high during this phase of power-up. once the 100s delay has been satisfied, cke high and the precharge command can be applied (set up and held with respect to a positive edge of clk). both banks must then be precharged, thereby placing the device in the all banks idle state. once in the idle state, two auto refresh cycles must be performed. after the auto refresh cycles are complete, the sdram is ready for mode register pro- gramming. because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. register definition mode register the mode register is used to define the specific mode of operation of the sdram. this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode, and a write burst mode, as shown in figure 1. the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power. mode register bits m0-m2 specify the burst length, m3 specifies the type of burst (sequential or interleaved), m4-m6 specify the cas latency, m7 and m8 specify the operating mode, m9 specifies the write burst mode, and m10 and m11 are reserved for future use. the mode register must be loaded when both banks are idle, and the controller must wait the specified time before initiating the subsequent operation. violating ei- ther of these requirements will result in unspecified op- eration. burst length read and write accesses to the sdram are burst ori- ented, with the burst length being programmable, as shown in figure 1. the burst length determines the maxi- mum number of column locations that can be accessed for a given read or write command. burst lengths of 1, 2, 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full-page burst is available for the sequential type. the full-page burst is used in conjunction with the burst terminate com- mand to generate arbitrary burst lengths. reserved states should not be used, as unknown op- eration or incompatibility with future versions may re- sult. when a read or write command is issued, a block of columns equal to the burst length is effectively se- lected. all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. the block is uniquely selected by a1-a9 (a9 is dont care for x8) when the burst length is set to two; by a2-a9 (a9 is dont care for x8) when the burst length is set to four; and by a3-a9 (a9 is dont care for x8) when the burst length is set to eight. the remaining (least significant) address bit(s) is (are) used to select the starting location within the block. full-page bursts wrap within the page if the boundary is reached. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit m3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting col- umn address, as shown in table 1.
8 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram note: 1. for a burst length of two, a1-a9 select the block of two burst (a9 is a dont care for x8); a0 selects the starting column within the block. 2. for a burst length of four, a2-a9 select the block of four burst (a9 is a dont care for x8); a0-a1 select the starting column within the block. 3. for a burst length of eight, a3-a9 select the block of eight burst (a9 is a dont care for x8); a0-a2 select the starting column within the block. 4. for a full-page burst, the full row is selected and a0-a9 select the starting column (a9 is a dont care for x8). 5. whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 6. for a burst length of one, a0-a9 select the unique column to be accessed (a9 is a dont care for x8), and mode register bit m3 is ignored. table 1 burst definition burst starting column order of accesses within a burst length address: type = sequential type = interleaved a0 2 0 0-1 0-1 1 1-0 1-0 a1 a0 0 0 0-1-2-3 0-1-2-3 4 0 1 1-2-3-0 1-0-3-2 1 0 2-3-0-1 2-3-0-1 1 1 3-0-1-2 3-2-1-0 a2 a1 a0 0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 8 0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3 1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2 1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1 1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 full x4: n = a0-a9 cn, cn+1, cn+2 page x8: n = a0-a8 cn+3, cn+4... not supported (x4: 1,024) (location 0-1,023) cn-1, (x8: 512) (location 0-511) cn m2 0 0 0 0 1 1 1 1 m1 0 0 1 1 0 0 1 1 m0 0 1 0 1 0 1 0 1 m3 = 0 1 2 4 8 reserved reserved reserved full page m3 = 1 1 2 4 8 reserved reserved reserved reserved operating mode standard operation all other states reserved 0 - 0 - defined - 0 1 burst type sequential interleaved cas latency reserved 1 2 3 reserved reserved reserved reserved m6 0 0 0 0 1 1 1 1 m4 0 1 0 1 0 1 0 1 m5 0 0 1 1 0 0 1 1 burst length burst length cas latency bt a9 a7 a6 a5 a4 a3 a8 a2 a1 a0 mode register (mx) address bus 9 7 654 3 8 2 1 0 m3 m6-m0 m8 m7 op mode a10 ba 10 11 reserved* wb 0 1 write burst mode programmed burst length single location access m9 *should program m11, m10 = 0, 0 to ensure compatibility with future devices. figure 1 mode register definition
9 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram allowable operating frequency (mhz) cas cas cas speed latency = 1 latency = 2 latency = 3 -8d/e 33 100 125 -8a/b/c 33 83 125 -10 33 66 100 cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data. the latency can be set to 1, 2, or 3 clocks. if a read command is registered at clock edge n , and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier ( n + m - 1) and, provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t0, and the latency is programmed to two clocks, the dqs will start driving after t1 and the data will be valid by t2, as shown in figure 2. table 2 below indicates the operating frequen- cies at which each cas latency setting can be used. reserved states should not be used, as unknown op- eration or incompatibility with future versions may re- sult. operating mode the normal operating mode is selected by setting m7 and m8 to zero; the other combinations of values for m7 and m8 are reserved for future use and/or test modes. the programmed burst length applies to both read and write bursts. test modes and reserved states should not be used because unknown operation or incompatibility with fu- ture versions may result. write burst mode when m9 = 0, the burst length programmed via m0- m2 applies to both read and write bursts; when m9 = 1, the programmed burst length applies to read bursts, but write accesses are single-location (nonburst) accesses. clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop dont care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop figure 2 cas latency table 2 cas latency
10 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram truth table 1 C commands and dqm operation (note: 1) name (function) cs# ras# cas# we# dqm addr dqs notes command inhibit (nop) h xxxx x x no operation (nop) l h h h x x x active (select bank and activate row) l l h h x bank/row x 3 read (select bank and column and start read burst) l h l h x bank/col x 4 write (select bank and column and l h l l x bank/col valid 4 start write burst) burst terminate l h h l x x active precharge (deactivate row in bank or banks) l l h l x code x 5 auto refresh or l l l h x x x 6, 7 self refresh (enter self refresh mode) load mode register l l l l x op-code x 2 write enable/output enable CCCCl C active 8 write inhibit/output high-z CCCCh C high-z 8 following the operation section; these tables provide current state/next state information. commands truth table 1 provides a quick reference of avail- able commands. this is followed by a written description of each command. two additional truth tables appear note: 1. cke is high for all commands shown except self refresh. 2. a0-a10 and ba define the op-code written to the mode register. 3. a0-a10 provide row address, and ba determines which bank is made active (ba low = bank 0; ba high = bank 1). 4. a0-a9 (a9 is a dont care for x8) provide column address; a10 high enables the auto precharge feature (nonpersis- tent), while a10 low disables the auto precharge feature; ba determines which bank is being read from or written to (ba low = bank 0; ba high = bank 1). 5. for a10 low, ba determines which bank is being precharged (ba low = bank 0; ba high = bank 1); for a10 high, both banks are precharged and ba is a dont care. 6. this command is auto refresh if cke is high, self refresh if cke is low. 7. internal refresh counter controls row addressing; all inputs and i/os are dont care except for cke. 8. activates or deactivates the dqs during writes (zero-clock delay) and reads (two-clock delay).
11 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram command inhibit the command inhibit function prevents new com- mands from being executed by the sdram, regardless of whether the clk signal is enabled. the sdram is effec- tively deactivated, or deselected. no operation (nop) the no operation (nop) command is used to per- form a nop to an sdram which is selected (cs# is low). this prevents unwanted commands from being regis- tered during idle or wait states. load mode register the mode register is loaded via inputs a0-a10 and ba. see mode register heading in register definition section. the load mode register command can only be issued when both banks are idle, and a subsequent executable command cannot be issued until t mrd is met. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba input selects the bank, and the address provided on inputs a0-a10 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge com- mand must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba input selects the bank, and the address provided on inputs a0-a9 (a9 is a dont care on x8) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the read burst; if auto precharge is not selected, the row will remain open for subsequent accesses. read data appears on the dqs, subject to the logic level on the dqm input, two clocks earlier. if the dqm signal was regis- tered high, the dqs will be high-z two clocks later; if the dqm signal was registered low, the dqs will provide valid data. write the write command is used to initiate a burst write access to an active row. the value on the ba input selects the bank, and the address provided on inputs a0-a9 (a9 is a dont care on x8) selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to the memory array subject to the dqm input logic level appearing coinci- dent with the data. if the dqm signal is registered low, the corresponding data will be written to memory; if the dqm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in both banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or both banks are to be precharged, and in the case where only one bank is to be precharged, input ba selects the bank. otherwise ba is treated as a dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, without requiring an explicit command. this is accom- plished by using a10 to enable auto precharge in con- junction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write command is automatically performed upon completion of the read or write burst, except in the full-page burst mode, where auto precharge does not apply. auto precharge is nonpersistent in that it is either enabled or disabled for each individual read or write command. auto precharge ensures that the precharge is initi- ated at the earliest valid stage within a burst. the user must not issue another command until the precharge time ( t rp) is completed. this is determined as if an ex- plicit precharge command was issued at the earliest possible time, as described for each burst type in the operation section of this data sheet. burst terminate the burst terminate command is used to trun- cate either fixed-length or full-page bursts. the most recently registered read or write command prior to the burst terminate command will be truncated, as shown in the operation section of this data sheet.
12 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram auto refresh auto refresh is used during normal operation of the sdram and is analagous to cas#-before-ras# (cbr) refresh in conventional drams. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits dont care during an auto refresh command. the micron 16mb sdram requires all of its 4,096 rows to be refreshed every 64ms ( t ref). providing a distributed auto refresh command every 15.6s will meet the refresh require- ment and ensure that each row is refreshed. alterna- tively, all 4,096 auto refresh commands can be is- sued in a burst at the minimum cycle rate ( t rc) once every 64ms. self refresh the self refresh command can be used to re- tain data in the sdram, even if the rest of the system is powered down. when in the self refresh mode, the sdram retains data without external clocking. the self re- fresh command is initiated like an auto refresh command except cke is disabled (low). once the self refresh command is registered, all the inputs to the sdram become dont care, with the exception of cke, which must remain low. once self refresh mode is engaged, the sdram pro- vides its own internal clocking, causing it to perform its own auto refresh cycles. the sdram must remain in self refresh mode for a minimum period equal to t ras and may remain in self refresh mode for an indefinite period beyond that. the procedure for exiting self refresh requires a se- quence of commands. first, clk must be stable prior to cke going back high. once cke is high, the sdram must have nop commands issued (a minimum of two clocks) for t xsr because time is required for the comple- tion of any internal refresh in progress. a burst of 4,096 auto refresh cycles should be completed just prior to entering and just after exiting the self refresh mode.
13 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram operation bank/row activation before any read or write commands can be issued to a bank within the sdram, a row in that bank must be opened. this is accomplished via the active com- mand, which selects both the bank and the row to be activated. after opening a row (issuing an active command), a read or write command may be issued to that row, subject to the t rcd specification. t rcd (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which a read or write com- mand can be entered. for example, a t rcd specification of 30ns with a 90 mhz clock (11.11ns period) results in 2.7 clocks, rounded to 3. this is reflected in figure 4, which covers any case where 2 < t rcd (min)/ t ck < 3. (the same procedure is used to convert other specification limits from time units to clock cycles.) a subsequent active command to a different row in the same bank can only be issued after the previous active row has been closed (precharged). the mini- mum time interval between successive active com- mands to the same bank is defined by t rc. a subsequent active command to the other bank can be issued while the first bank is being accessed, resulting in a reduction of total row access overhead. the minimum time interval between successive active com- mands to different banks is defined by t rrd. cs# we# cas# ras# cke clk a0-a10 ba row address high bank 0 bank 1 figure 3 activating a specific row in a specific bank clk t2 t1 t3 t0 t command nop active read or write t4 nop rcd dont care figure 4 example: meeting t rcd (min) when 2 < t rcd (min)/ t ck < 3
14 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram upon completion of a burst, assuming no other com- mands have been initiated, the dqs will go high-z. a full- page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) a fixed-length read burst may be followed by, or truncated with, a read burst (provided that auto precharge is not activated), and a full-page read burst can be truncated with a subsequent read burst. in either case, a continuous flow of data can be maintained. the first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst that is being truncated. the new read command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is reads read bursts are initiated with a read command, as shown in figure 5 (a9 is a dont careon x8). the starting column and bank addresses are pro- vided with the read command, and auto precharge is either enabled or disabled for that burst access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the ge- neric read commands used in the following illustra- tions, auto precharge is disabled. during read bursts, the valid data-out element from the starting column address will be available following the cas latency after the read command. each subse- quent data-out element will be valid by the next positive clock edge. figure 6 shows general timing for each pos- sible cas latency setting. cs# we# cas# ras# cke clk column address a0-a9 a10 ba bank 0 bank 1 high enable auto precharge disable auto precharge ( a9 is a dont care for x8) figure 5 read command clk dq t2 t1 t3 t0 cas latency = 3 lz d out t oh t command nop read t ac nop t4 nop dont care undefined clk dq t2 t1 t0 cas latency = 1 lz d out t oh t command nop read t ac clk dq t2 t1 t3 t0 cas latency = 2 lz d out t oh t command nop read t ac nop figure 6 cas latency
15 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram shown in figure 7 for cas latencies of one, two and three; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. the micron 16mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architec- figure 7 consecutive read bursts ture. a read command can be initiated on any clock cycle following a previous read command. full-speed random read accesses can be performed to the same bank, as shown in figure 8, or each subsequent read may be performed to a different bank. clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop nop nop bank, col n dont care nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 0 cycles note: each read command may be to either bank. dqm is low. cas latency = 1 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read x = 1 cycle cas latency = 2 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop bank, col b d out n + 1 d out n + 2 d out n + 3 d out b read nop t7 x = 2 cycles cas latency = 3
16 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram figure 8 random read accesses clk dq t2 t1 t4 t3 t6 t5 t0 command address read nop nop bank, col n dont care d out n d out a d out x d out m read note: each read command may be to either bank. dqm is low. read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t5 t0 command address read nop bank, col n d out a d out x d out m read read read nop bank, col a bank, col x bank, col m clk dq d out n t2 t1 t4 t3 t0 command address read nop bank, col n d out a d out x d out m read read read bank, col a bank, col x bank, col m cas latency = 1 cas latency = 2 cas latency = 3
17 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram a fixed-length read burst may be followed by, or truncated with, a write burst (provided that auto precharge was not activated), and a full-page read burst may be truncated by a write burst. the write burst may be initiated on the clock edge immediately following the last (or last desired) data element from the read burst, provided that i/o contention can be avoided. in a given system design, there may be a possibility that the device driving the input data will go low-z before the sdram dqs go high-z. in this case, a single-cycle delay should occur between the last read data and the write command. the dqm input is used to avoid i/o contention, as shown in figures 9 and 10. the dqm signal must be asserted (high) at least two clocks prior to the write command (dqm latency is two clocks for output buffers) to suppress data-out from the read. once the write command is registered, the dqs will go high-z (or re- main high-z) regardless of the state of the dqm signal. the dqm signal must be de-asserted prior to the write command (dqm latency is zero clocks for input buffers) to ensure that the written data is not masked. figure 9 shows the case where the clock frequency allows for bus contention to be avoided without adding a nop cycle, and figure 10 shows the case where the additional nop is needed. read nop nop nop nop dqm clk dq d out n t2 t1 t4 t3 t0 command address bank, col n write d in b bank, col b t5 ds t hz t dont care note: a cas latency of three is used for illustration. the read command may be to either bank, and the write command may be to either bank. figure 10 read to write with extra clock cycle figure 9 read to write read nop nop write nop clk t2 t1 t4 t3 t0 dqm dq d out n command d in b address bank, col n bank, col b ds t hz t t ck note: a cas latency of three and a burst of two or more is used for illustration. the read command may be to either bank, and the write command may be to either bank. if a burst of one is used, then dqm is not required.
18 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram figure 11 read to precharge a fixed-length read burst may be followed by, or truncated with, a precharge command to the same bank (provided that auto precharge was not activated), and a full-page burst may be truncated with a precharge command to the same bank. the precharge command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 11 for each possible cas latency; data element n + 3 is either the last of a burst of four or the last desired of a longer burst. follow-ing the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. note that part of the row precharge time is hidden during the access of the last data element(s). in the case of a fixed-length burst being executed to completion, a precharge command issued at the op- timum time (as described above) provides the same op- clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank a, col n nop d out n + 1 d out n + 2 d out n + 3 precharge active t rp t7 bank a, row bank (a or all) dont care x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles bank a, col n bank a, row bank (a or all) bank a, col n bank a, row bank (a or all)
19 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram eration that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the com- mand and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate fixed-length or full-page bursts. the auto precharge com- mand does not truncate fixed-length bursts and does not apply to full-page bursts. full-page read bursts can be truncated with the burst terminate command, and fixed-length read bursts may be truncated with a burst terminate command, provided that auto precharge was not acti- vated. the burst terminate command should be issued x cycles before the clock edge at which the last desired data element is valid, where x equals the cas latency minus one. this is shown in figure 12 for each possible cas latency; data element n + 3 is the last de- sired data element of a longer burst. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop t7 dont care note: dqm is low. clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n nop d out n + 1 d out n + 2 d out n + 3 burst terminate nop x = 0 cycles cas latency = 1 x = 1 cycle cas latency = 2 cas latency = 3 x = 2 cycles figure 12 terminating a read burst
20 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram writes write bursts are initiated with a write command, as shown in figure 13 (a9 is a dont care on x8). the starting column and bank addresses are pro- vided with the write command and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the ge- neric write commands used in the following illustra- tions, auto precharge is disabled. during write bursts, the first valid data-in element will be registered coincident with the write command. subsequent data elements will be registered on each successive positive clock edge. upon completion of a fixed-length burst, assuming no other commands have been initiated, the dqs will remain high-z, and any additional input data will be ignored (see figure 14). a full-page burst will continue until terminated. (at the end of the page, it will wrap to column 0 and continue.) a fixed-length write burst may be followed by, or truncated with, a write burst (provided that auto precharge was not activated), and a full-page write burst can be truncated with a subsequent write burst. the new write command can be issued on any clock following the previous write command, and the data figure 15 write to write figure 13 write command provided coincident with the new command applies to the new command. an example is shown in figure 15. data n + 1 is either the last of a burst of two or the last desired of a longer burst. the micron 16mb sdram uses a pipelined architecture and therefore does not require the 2 n rule associated with a prefetch architecture. a write command can be initiated on any clock cycle clk dq t2 t1 t0 command address nop dont care write write bank, col n bank, col b d in n d in n + 1 d in b note: dqm is low. each write command may be to either bank. clk dq d in n t2 t1 t3 t0 command address nop nop write d in n + 1 nop bank, col n note: burst length = 2. dqm is low. figure 14 write burst cs# we# cas# ras# cke clk column address a0-a9 a10 ba bank 0 bank 1 disable auto-precharge high enable auto-precharge ( a9 is a dont care for x8)
21 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram bank (provided that auto precharge was not activated), and a full-page write burst may be truncated with a precharge command to the same bank. the precharge command should be issued t wr after the clock edge at which the last desired input data element is registered. the two-clock write recovery version (a2) requires at least two clocks, regardless of frequency, as well as t wr being met. in addition, when truncating a write burst, the dqm signal must be used to mask input data for the clock edge on which the precharge command is entered. an example is shown in figure 18. data n + 1 is either the last of a burst of two or the last desired of a longer burst. following the precharge command, a subsequent command to the same bank cannot be issued until t rp is met. in the case of a fixed-length burst being executed to completion, a precharge command issued at the op- timum time (as described above) provides the same op- eration that would result from the same fixed-length burst with auto precharge. the disadvantage of the precharge command is that it requires that the com- mand and address buses be available at the appropriate time to issue the command; the advantage of the precharge command is that it can be used to truncate following a previous write command. full-speed ran- dom write accesses can be performed to the same bank, as shown in figure 16, or each subsequent write may be performed to a different bank. a fixed-length write burst may be followed by, or truncated with, a read burst (provided that auto precharge was not activated), and a full-page write burst can be truncated with a subsequent read burst. once the read command is registered, the data inputs will be ignored, and writes will not be executed. an example is shown in figure 17. data n + 1 is either the last of a burst of two or the last desired of a longer burst. a fixed-length write burst may be followed by, or truncated with, a precharge command to the same dqm clk dq t2 t1 t4 t3 t0 command address bank a , col n t5 nop write precharge nop nop d in n d in n + 1 active t rp bank ( a or all) t wr bank a , row dqm dq command address bank a , col n nop write precharge nop nop d in n d in n + 1 active t rp dont care bank ( a or all) t wr note: dqm could remain low in this example if the write burst is a fixed length of two. bank a , row t6 nop nop t wr@ t ck 15ns t wr@ t ck < 15ns figure 18 write to precharge clk dq d in n t2 t1 t3 t0 command address write bank, col n d in a d in x d in m write write write bank, col a bank, col x bank, col m note: each write command may be to either bank. dqm is low. figure 16 random write cycles clk dq t2 t1 t3 t0 command address nop write bank, col n d in n d in n + 1 d out b read nop nop bank, col b nop d out b + 1 t4 t5 note: the write command may be to either bank, and the read command may be to either bank. dqm is low. cas latency = 2 for illustration. figure 17 write to read
22 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram fixed-length or full-page bursts. the auto precharge command does not truncate fixed-length bursts and does not apply to full page bursts. fixed-length or full-page write bursts can be trun- cated with the burst terminate command. when truncating a write burst, the input data applied coinci- dent with the burst terminate command will be ignored. the last data written (provided that dqm is figure 20 precharge command t ras t rcd t rc all banks idle input buffers gated off exit power-down mode. ( ) ( ) ( ) ( ) ( ) ( ) t cks t cks command nop active enter power-down mode. nop clk cke ( ) ( ) ( ) ( ) dont care coming out of a power-down sequence (active), t cks (cke setup time) must be greater than or equal to 3ns. figure 21 power-down cs# we# cas# ras# cke clk a10 ba bank 1 high bank 0 and 1 bank 0 or 1 bank 0 a0-a9 figure 19 terminating a write burst clk dq t2 t1 t0 command address bank, col n write burst terminate next command d in n (address) (data) low at that time) will be the input data applied one clock previous to the burst terminate command. this is shown in figure 19, where data n is the last desired data element of a longer burst. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in both banks. the bank(s) will be available for a subsequent row access some specified time ( t rp) after the precharge command is issued. input a10 determines whether one or both banks are to be precharged, and in the case where only one bank is to be precharged, input ba selects the bank. when both banks are to be precharged, input ba is treated as a dont care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. power-down power-down occurs if cke is registered low coinci- dent with a nop or command inhibit, when no ac- cesses are in progress. if power-down occurs when both banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in either bank, this mode is referred to as active power-down. entering power-down deactivates the in- put and output buffers, excluding cke, for maximum power savings while in standby. the device may not remain in the power-down state longer than the refresh period (64ms) since no refresh operations are performed in this mode. the power-down state is exited by registering a nop or command inhibit and cke high at the de- sired clock edge (meeting t cks).
23 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram dq command address write bank, col n d in n nop nop clk t2 t1 t4 t3 t5 t0 cke internal clock nop d in n + 1 d in n + 2 note: for this example, burst length = 4 or greater, and d q m is low. figure 22 clock suspend during write burst clk dq d out n t2 t1 t4 t3 t6 t5 t0 command address read nop nop nop bank, col n dont care nop d out n + 1 d out n + 2 d out n + 3 note: for this example, cas latency = 2, burst length = 4 or greater, and dqm is low. cke internal clock nop figure 23 clock suspend during read burst clock suspend the clock suspend mode occurs when a column ac- cess/burst is in progress and cke is registered low. in the clock suspend mode, the internal clock is deacti- vated, freezing the synchronous logic. for each positive clock edge on which cke is sampled low, the next internal positive clock edge is suspended. any command or data present on the input pins at the time of a suspended internal clock edge is ignored; any data present on the dq pins remains driven; and burst counters are not incremented, as long as the clock is suspended (see examples in figures 22 and 23). clock suspend mode is exited by registering cke high; the internal clock and related operation will re- sume on the subsequent positive clock edge. burst read/single write the burst read/single write mode is entered by pro- gramming the write burst mode bit (m9) in the mode register to a logic 1. in this mode, all write commands result in the access of a single column location (burst of one), regardless of the programmed burst length. read commands access columns according to the pro- grammed burst length and sequence, just as in the nor- mal mode of operation (m9 = 0).
24 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram concurrent auto precharge an access command (read or write) to another bank while an access command with auto precharge enabled is executing is not allowed by sdrams, unless the sdram supports concurrent auto precharge. micron sdrams support concurrent auto precharge. four cases where concurrent auto precharge occurs are defined below. read with auto precharge 1. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 24). 2. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 25). clk dq d out a t2 t1 t4 t3 t6 t5 t0 command read - ap bank n nop nop nop nop d out a + 1 d out d d out d + 1 nop t7 bank n cas latency = 3 (bank m ) bank m address idle nop note: d q m is low. bank n , col a bank m , col d read - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active read with burst of 4 precharge rp - bank n t rp - bank m cas latency = 3 (bank n ) figure 24 read with auto precharge interrupted by a read clk dq d out a t2 t1 t4 t3 t6 t5 t0 command nop nop nop nop d in d + 1 d in d d in d + 2 d in d + 3 nop t7 bank n bank m address idle nop dqm note: 1. dqm is high at t2 to prevent d out - a +1 from contending with d in - d at t4. bank n , col a bank m , col d write - ap bank m internal states t page active read with burst of 4 interrupt burst, precharge page active write with burst of 4 write-back rp - bank n t wr - bank m cas latency = 3 (bank n ) read - ap bank n 1 dont care figure 25 read with auto precharge interrupted by a write
25 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram write with auto pr echarge 3. interrupted by a read (with or without auto precharge): a read to bank m will interrupt a write on bank n when registered, with the data-out appear- ing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 26). 4. interrupted by a write (with or without auto precharge): a write to bank m will interrupt a write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid data write to bank n will be data registered one clock prior to a write to bank 1 (figure 27). clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in a + 1 d in a nop nop t7 bank n bank m address note: 1. dqm is low. bank n , col a bank m , col d read - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active read with burst of 4 t t rp - bank m d out d d out d + 1 cas latency = 3 (bank m ) rp - bank n wr - bank n figure 26 write with auto precharge interrupted by a read dont care clk dq t2 t1 t4 t3 t6 t5 t0 command write - ap bank n nop nop nop nop d in d + 1 d in d d in a + 1 d in a + 2 d in a d in d + 2 d in d + 3 nop t7 bank n bank m address nop note: 1. dqm is low. bank n , col a bank m , col d write - ap bank m internal states t page active write with burst of 4 interrupt burst, write-back precharge page active write with burst of 4 write-back wr - bank n t rp - bank n t wr - bank m figure 27 write with auto precharge interrupted by a write
26 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram truth table 2 C cke (notes: 1-4) cke n-1 cke n current state command n action n notes l l power-down x maintain power-down self refresh x maintain self refresh clock suspend x maintain clock suspend l h power-down command inhibit or nop exit power-down 5 self refresh command inhibit or nop exit self refresh 6 clock suspend x exit clock suspend 7 h l both banks idle command inhibit or nop power-down entry both banks idle auto refresh self refresh entry reading or writing valid clock suspend entry h h see truth table 3 note: 1. cke n is the logic state of cke at clock edge n; cke n-1 was the state of cke at the previous clock edge. 2. current state is the state of the sdram immediately prior to clock edge n . 3. command n is the command registered at clock edge n and action n is a result of command n . 4. all states and sequences not shown are illegal or reserved. 5. exiting power-down at clock edge n will put the device in the all banks idle state in time for clock edge n + 1 (provided that t cks is met). 6. exiting self refresh at clock edge n will put the device in the all banks idle state once t xsr is met. command inhibit or nop commands should be issued on any clock edges occurring during the t xsr period. a minimum of two nop commands must be provided during the t xsr period. 7. after exiting clock suspend at clock edge n , the device will resume operation and recognize the next command at clock edge n + 1 .
27 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram truth table 3 C current state bank n - command to bank n (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) l l h h active (select bank and activate row) idle l l l h auto refresh 7 llll load mode register 7 l l h l precharge 11 l h l h read (select bank and column and start read burst) 10 row active l h l l write (select bank and column and start write burst) 10 l l h l precharge (deactivate row in bank or banks) 8 read l h l h read (select bank and column and start new read burst) 10 (auto- l h l l write (select bank and column and start write burst) 10 precharge l l h l precharge (truncate read burst, start precharge) 8 disabled) l h h l burst terminate 9 write l h l h read (select bank and column and start read burst) 10 (auto- l h l l write (select bank and column and start new write burst) 10 precharge l l h l precharge (truncate write burst, start precharge) 8 disabled) l h h l burst terminate 9 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table is bank-specific, except where noted; i.e., the current state is for a specific bank, and the commands shown are those allowed to be issued to that bank when it is in that state. exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged and t rp has been met. row active: a row in the bank has been activated and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 4. the following states must not be interrupted by a command issued to the same bank. command inhibit or nop commands or allowable commands to the other bank should be issued on any clock edge occurring during these states. allowable commands to the other bank are determined by its current state and truth table 3, and according to truth table 4. precharging: starts with registration of a precharge command and ends when t rp is met. once t rp is met, the bank will be in the idle state. row activating: starts with registration of an active command and ends when t rcd is met. once t rcd is met, the bank will be in the row active state. read w/auto- precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto- precharge enabled: starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
28 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram note (continued): 5. the following states must not be interrupted by any executable command; command inhibit or nop commands must be applied on each positive clock edge during these states. refreshing: starts with registration of an auto refresh command and ends when t rc is met. once t rc is met, the sdram will be in the all banks idle state. accessing mode register: starts with registration of a load mode register command and ends when t mrd has been met. once t mrd is met, the sdram will be in the all banks idle state. 6. all states and sequences not shown are illegal or reserved. 7. not bank-specific; requires that both banks are idle. 8. may or may not be bank-specific; if both banks are to be precharged, both must be in a valid state for precharging. 9. not bank-specific; burst terminate affects the most recent read or write burst, regardless of bank. 10. reads or writes listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 11. does not affect the state of the bank and acts as a nop to that bank.
29 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram truth table 4 C current state bank n - command to bank m (notes: 1-6; notes appear below and on next page) current state cs# ras# cas# we# command (action) notes any h x x x command inhibit (nop/continue previous operation) l h h h no operation (nop/continue previous operation) idle xxxx any command otherwise allowed to bank m row l l h h active (select and activate row) activating, l h l h read (select column and start read burst) 7 active, or l h l l write (select column and start write burst) 7 precharging l l h l precharge read l l h h active (select and activate row) (auto- l h l h read (select column and start new read burst) 7, 10 precharge l h l l write (select column and start write burst) 7, 11 disabled) l l h l precharge 9 write l l h h active (select and activate row) (auto- l h l h read (select column and start read burst) 7, 12 precharge l h l l write (select column and start new write burst) 7, 13 disabled) l l h l precharge 9 read l l h h active (select and activate row) (with auto- l h l h read (select column and start new read burst) 7, 8, 14 precharge) l h l l write (select column and start write burst) 7, 8, 15 l l h l precharge 9 write l l h h active (select and activate row) (with auto- l h l h read (select column and start read burst) 7, 8, 16 precharge) l h l l write (select column and start new write burst) 7, 8, 17 l l h l precharge 9 note: 1. this table applies when cke n-1 was high and cke n is high (see truth table 2) and after t xsr has been met (if the previous state was self refresh). 2. this table describes alternate bank operation, except where noted; i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). exceptions are covered in the notes below. 3. current state definitions: idle: the bank has been precharged, and t rp has been met. row active: a row in the bank has been activated, and t rcd has been met. no data bursts/accesses and no register accesses are in progress. read: a read burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. write: a write burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. read w/auto- precharge enabled: starts with registration of a read command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state. write w/auto- precharge enabled: starts with registration of a write command with auto precharge enabled, and ends when t rp has been met. once t rp is met, the bank will be in the idle state.
30 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram note (continued): 4. auto refresh, self refresh, and load mode register commands may only be issued when all banks are idle. 5. a burst terminate command cannot be issued to another bank; it applies to the bank represented by the current state only. 6. all states and sequences not shown are illegal or reserved. 7. reads or writes to bank m listed in the command (action) column include reads or writes with auto precharge enabled and reads or writes with auto precharge disabled. 8. concurrent auto precharge: bank n will initiate the auto precharge command when its burst has been inter- rupted by bank ms burst. 9. burst in bank n continues as initiated. 10. for a read without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later (figure 7). 11. for a read without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered (figures 9 and 10). dqm should be used one clock prior to the write command to prevent bus contention. 12. for a write without auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered (figure 17), with the data-out appearing cas latency later. the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 13. for a write without auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered (figure 15). the last valid write to bank n will be data-in registered one clock prior to the read to bank m . 14. for a read with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the read on bank n , cas latency later. the precharge to bank n will begin when the read to bank m is registered (figure 24). 15. for a read with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the read on bank n when registered. dqm should be used two clocks prior to the write command to prevent bus contention. the precharge to bank n will begin when the write to bank m is registered (figure 25). 16. for a write with auto precharge interrupted by a read (with or without auto precharge), the read to bank m will interrupt the write on bank n when registered, with the data-out appearing cas latency later. the precharge to bank n will begin after t wr is met, where t wr begins when the read to bank m is registered. the last valid write to bank n will be data-in registered one clock prior to the read to bank m (figure 26). 17. for a write with auto precharge interrupted by a write (with or without auto precharge), the write to bank m will interrupt the write on bank n when registered. the precharge to bank n will begin after t wr is met, where t wr begins when the write to bank m is registered. the last valid write to bank n will be data registered one clock prior to the write to bank m (figure 27).
31 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram absolute maximum ratings* voltage on v dd /v dd q supply relative to v ss ............................................ -1v to +4.6v voltage on inputs, nc or i/o pins relative to v ss ............................................ -1v to +4.6v operating temperature, t a (ambient) ....... 0c to +70c storage temperature (plastic) .............. -55c to +150c power dissipation ......................................................... 1w *stresses greater than those listed under absolute maxi- mum ratings may cause permanent damage to the device. this is a stress rating only, and functional opera- tion of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maxi- mum rating conditions for extended periods may affect reliability. dc electrical characteristics and operating conditions (notes: 1, 6; notes appear on page 34) (0c t a 70c; v dd /v dd q = +3.3v 0.3v) parameter/condition symbol min max units notes supply voltage v dd /v dd q 3 3.6 v input high voltage: logic 1; all inputs v ih 2v dd + 0.3 v 23 input low voltage: logic 0; all inputs v il -0.5 0.8 v 23 input leakage current: any input 0v v in v dd i i -5 5 a (all other pins not under test = 0v) output leakage current: dqs are disabled; 0v v out v dd qi oz -5 5 a output levels: v oh 2.4 C v output high voltage (i out = -2ma) output low voltage (i out = 2ma) v ol C 0.4 v i cc specifications and conditions (notes: 1, 6, 11, 13; notes appear on page 34) (0c t a 70c; v dd /v dd q = +3.3v 0.3v) parameter/condition symbol -8b -10 units notes operating current: active mode; i cc 1 105 90 ma 3, 18, burst = 2; read or write; t rc = t rc (min); 19 cas latency = 3; t ck = 10ns (15ns for -10) standby current: power-down mode; all banks idle; i cc 2 32ma cke = low; t ck = 10ns (15ns for -10) standby current: active mode; i cc 3 45 40 ma 3, 12, cke = high; cs# = high; t ck = 10ns (15ns for -10); 19 all banks active after t rcd met; no accesses in progress operating current: burst mode; continuous burst; i cc 4 125 85 ma 3, 18, read or write; t ck = 10ns (15ns for -10); all banks active; 19 cas latency = 3 auto refresh current: i cc 5 95 85 ma 3, 12, t rc = t rc (min); cas latency = 3; 18, 19 cke = high; cs# = high; t ck = 10ns (15ns for -10) self refresh current: cke 0.2v i cc 6 12ma4 max
32 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram electrical characteristics and recommended ac operating conditions (notes: 5, 6, 8, 9, 11; notes appear on page 34) (0c t a +70c) ac characteristics -8b -10 parameter symbol min max min max units notes access time from clk (pos. edge) cl = 3 t ac (3) 6 7.5 ns cl = 2 t ac (2) 9 9 ns 22 cl = 1 t ac (1) 27 27 ns 22 address hold time t ah 1 1 ns address setup time t as 2 3 ns clk high-level width t ch 3 3.5 ns clk low-level width t cl 3 3.5 ns clock cycle time cl = 3 t ck (3) 8 10 ns 24 cl = 2 t ck (2) 12 15 ns 22, 24 cl = 1 t ck (1) 30 30 ns 24 cke hold time t ckh 1 1 ns cke setup time t cks 2 3 ns cs#, ras#, cas#, we#, dqm hold time t cmh 1 1 ns cs#, ras#, cas#, we#, dqm setup time t cms 2 3 ns data-in hold time t dh 1 1 ns data-in setup time t ds 2 3 ns data-out high-impedance time cl = 3 t hz (3) 6 8 ns 10 cl = 2 t hz (2) 7 10 ns 10 cl = 1 t hz (1) 15 15 ns 10 data-out low-impedance time t lz 1 2 ns data-out hold time t oh 3 3 ns active to precharge command t ras 50 120,000 60 120,000 ns auto refresh, active command period t rc 80 90 ns 22 active to read or write delay t rcd 20 30 ns 22 refresh period (2,048 or 4,096 rows) t ref 64 64 ms precharge command period t rp 24 30 ns 22 active bank a to active bank b command t rrd 20 20 ns transition time t t 0.3 1.2 1 1.2 ns 7 write recovery time a1 version t wr 1 1 t ck 25 10 10 ns 26 a2 version t wr 2 2 t ck 25 15 15 ns 26 exit self refresh to active command t xsr 80 90 ns 20 capacitance parameter symbol min max units notes input capacitance: clk c i 1 2.5 4.0 pf 2 input capacitance: all other input-only pins c i 2 2.5 5.0 pf 2 input/output capacitance: dqs c io 4.0 6.5 pf 2
33 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram ac functional characteristics (notes: 5, 6, 7, 8, 9, 11; notes appear on page 34) (0c t a +70c) parameter symbol -8b -10 units notes read/write command to read/write command t ccd 1 1 t ck 17 cke to clock disable or power-down entry mode t cked 1 1 t ck 14 cke to clock enable or power-down exit setup mode t ped 1 1 t ck 14 dqm to input data delay t dqd 0 0 t ck 17 dqm to data mask during writes t dqm 0 0 t ck 17 dqm to data high-impedance during reads t dqz 2 2 t ck 17 write command to input data delay t dwd 0 0 t ck 17 data-in to active command a1 version t dal 4 3 t ck 15, 21 a2 version t dal 5 4 t ck 15, 21 data-in to precharge command a1 version t dpl 1 1 t ck 16, 21 a2 version t dpl 2 2 t ck 16, 21 last data-in to burst stop command t bdl 1 1 t ck 17 last data-in to new read/write command t cdl 1 1 t ck 17 last data-in to precharge command a1 version t rdl 1 1 t ck 16, 21 a2 version t rdl 2 2 t ck 16, 21 load mode register command to active or refresh command t mrd 2 2 t ck 27 data-out to high-impedance from precharge command cl = 3 t roh (3) 33 t ck 17 cl = 2 t roh (2) 22 t ck 17 cl = 1 t roh (1) 11 t ck 17 electrical timing characteristics between -8 speed options (notes: 5, 6, 8, 9, 11, 24; notes appear on page 34) (0c t a +70c) ac characteristics -8e -8d -8c -8b -8a parameter sym min max min max min max min max min max units notes access time from clk (pos. edge) cl = 3 t ac (3)66666ns22 cl = 2 t ac (2)67999ns22 cl = 1 t ac (1) 27 27 27 27 27 ns 22 clock cycle time cl = 3 t ck (3)88888 ns22 cl = 2 t ck (2) 10 10 12 12 12 ns 22 cl = 1 t ck (1) 30 30 30 30 30 ns 22 active to read or write delay t rcd 20 20 20 20 24 ns 22 precharge command period t rp 20 20 20 24 24 ns 22 auto refresh, active command period t rc 70 70 70 80 80 ns 22 write recovery time a1 version t wr na na 1 1 1 t ck 21 a2 version t wr22222 t ck 21 100 mhz speed reference (cl- t rcd- t rp) 2-2-2 2-2-2 3-2-2 3-2-3 3-3-3 clks
34 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram 12. other input signals are allowed to transition no more than once in any 30ns period (20ns on -8) and are otherwise at valid v ih or v il levels. 13. i cc specifications are tested after the device is properly initialized. 14. timing actually specified by t cks; clock(s) specified as a reference only at minimum cycle rate. 15. timing actually specified by t wr plus t rp; clock(s) specified as a reference only at minimum cycle rate. 16. timing actually specified by t wr. 17. required clocks are specified by jedec functional- ity and are not dependent on any timing parameter. 18. the i cc current will decrease as the cas latency is reduced. this is due to the fact that the maximum cycle rate is slower as the cas latency is reduced. 19. address transitions average one transition every 30ns (20ns on -8). 20. clk must be toggled a minimum of two times during this period. 21. based on t ck = 100 mhz for -8 and 66 mhz for -10. 22. these five parameters vary between speed grades and define the differences between the -8 sdram speeds: -8a, -8b, -8c, -8d, and -8e. all other -8 timing parameters remain constant. 23. v ih overshoot: v ih (max) = v dd q + 2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. v il undershoot: v il (min) = -2v for a pulse width 10ns, and the pulse width cannot be greater than one third of the cycle rate. 24. the clock frequency must remain constant during access or precharge states (read, write, including t wr, and precharge commands). cke may be used to reduce the data rate. 25. auto precharge mode only. 26. precharge mode only. 27. jedec and pc100 specify three clocks. notes 1. all voltages referenced to v ss . 2. this parameter is sampled. v dd , v dd q = +3.3v; f = 1 mhz, t a = 25c; pin under test biased at 1.4v. 3. i cc is dependent on output loading and cycle rates. specified values are obtained with minimum cycle time and the outputs open. 4. enables on-chip refresh and address counters. 5. the minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range (0c t a 70c) is ensured. 6. an initial pause of 100s is required after power-up, followed by two auto refresh commands, before proper device operation is ensured. (v dd and v dd q must be powered up simultaneously. v ss and v ss q must be at same potential.) the two auto refresh command wake-ups should be repeated any time the t ref refresh requirement is exceeded. 7. ac characteristics assume t t = 1ns. 8. in addition to meeting the transition rate specifica- tion, the clock and cke must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 9. outputs measured at 1.5v with equivalent load: q 50pf 10. t hz defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . the last valid data element will meet t oh before going high-z. 11. ac timing and i cc tests have v il = 0v and v ih = 3v, with timing referenced to 1.5v crossover point.
35 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram initialize and load mode register t ch t cl t ck cke t0 clk t1 tn + 1 to + 1 tp + 1 tp + 2 tp + 3 command dq address bank, row t rc t mrd t rc auto refresh auto refresh program mode register. 1, 3, 4 t cmh t cms precharge all banks. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) t cks power-up: v dd and clk stable. t=100s t ah t as precharge nop nop auto refresh nop load mode register active nop nop nop code ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) auto refresh bank(s) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) high-z t ckh ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dont care undefined ( ) ( ) ( ) ( ) timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns -8b -10 symbol* min max min max units t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t mrd 3 22 t ck t rc 80 90 ns t rp 24 30 ns *cas latency indicated in parentheses. note: 1. the mode register may be loaded prior to the auto refresh cycles if desired. 2. if cs is high at clock high time, all commands applied are nop, with cke a dont care. 3. jedec and pc100 specify three clocks. 4. outputs are guaranteed high-z after command is issued.
36 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram power-down mode 1 t ch t cl t ck two clock cycles cke clk dq all banks idle, enter power-down mode. precharge all active banks. input buffers gated off while in power-down mode. exit power-down mode. ( ) ( ) ( ) ( ) dont care undefined t cks t cks command t cmh t cms precharge nop nop active nop ( ) ( ) ( ) ( ) all banks idle. address bank, row bank(s) ( ) ( ) ( ) ( ) high-z t ah t as t ckh t cks dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 tn + 1 tn + 2 note: 1. violating refresh requirements during power-down may result in a loss of data. t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units
37 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram clock suspend mode 1 t ch t cl t ck t ac t lz dqm clk a0-a9 dq ba a10 t oh d out m t ah t as t ah t as t ah t as bank t dh d in e t ac t hz d out m +1 command t cmh t cms t cmh t cms nop nop nop nop nop read write dont care undefined column e 2 cke t cks t ckh bank column m 2 t ds d in e +1 nop t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 timing parameters -8b -10 symbol* min max min max units t ac(3) 6 7.5 ns t ac(2) 9 9 ns t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns -8b -10 symbol* min max min max units t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t dh 1 1 ns t ds 2 3 ns t hz (3) 6 8 ns t hz (2) 7 10 ns t lz 1 2 ns t oh 3 3 ns *cas latency indicated in parentheses. note: 1. for this example, the burst length = 2, the cas latency = 3, and auto precharge is disabled. 2. column-address a9 is a dont care on x8 version.
38 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram auto refresh mode t ch t cl t ck cke clk dq t rc ( ) ( ) ( ) ( ) ( ) ( ) t rp ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) command t cmh t cms nop nop ( ) ( ) ( ) ( ) bank, row active auto refresh ( ) ( ) ( ) ( ) nop nop precharge precharge all active banks. auto refresh t rc high-z address bank(s) ( ) ( ) ( ) ( ) t ah t as t ckh t cks ( ) ( ) nop dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dont care undefined t0 t1 t2 tn +1 to + 1 ( ) ( ) ( ) ( ) timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns *cas latency indicated in parentheses. t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t rc 80 90 ns t rp 24 30 ns -8b -10 symbol* min max min max units
39 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram self refresh mode t ch t cl t ck t rp cke clk t0 t1 t2 tn + 1 to + 1 to + 2 dq enter self refresh mode. precharge all active banks. t xsr clk stable prior to exiting self refresh mode. exit self refresh mode. (restart refresh time base.) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dont care undefined command t cmh t cms auto refresh precharge nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) address bank(s) ( ) ( ) ( ) ( ) high-z t cks ah as auto refresh > t ras ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t ckh t cks dqm ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t t t cks t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t ras 50 120,000 60 120,000 ns t rp 24 30 ns t xsr 80 90 ns timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units
40 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram read C without auto precharge 1 bank 0 and 1 t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm cke clk a0-a9 dq ba a10 t oh d out m t ah t as t ah t as t ah t as row row bank bank(s) bank row row bank t hz t oh d out m+3 t ac t oh t ac t oh t ac d out m+2 d out m+1 command t cmh t cms precharge nop nop nop active nop read nop active disable auto precharge bank 0 or 1 dont care undefined column m 2 t ckh t cks t cmh t cms t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -8b -10 symbol* min max min max units t ac(3) 6 7.5 ns t ac(2) 9 9 ns t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t hz (3) 6 8 ns t hz (2) 7 10 ns t lz 1 2 ns t oh 3 3 ns t ras 50 120,000 60 120,000 ns t rc 80 90 ns t rcd 20 30 ns t rp 24 30 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. for this example, the burst length = 4, the cas latency = 2, and the read burst is followed by a manual precharge. 2. column-address a9 is a dont care on x8 version.
41 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram read C with auto precharge 1 enable auto precharge t ch t cl t ck t ac t lz t rp t ras t rcd cas latency t rc dqm cke clk a0-a9 dq ba a10 t oh d out m t ah t as t ah t as t ah t as row column m 2 row bank bank row row bank dont care undefined t hz t oh d out m+3 t ac t oh t ac t oh t ac d out m+2 d out m+1 command t cmh t cms t cmh t cms nop nop nop active nop read nop active nop t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -8b -10 symbol* min max min max units t ac(3) 6 7.5 ns t ac(2) 9 9 ns t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t hz (3) 6 8 ns t hz (2) 7 10 ns t lz 1 2 ns t oh 3 3 ns t ras 50 120,000 60 120,000 ns t rc 80 90 ns t rcd 20 30 ns t rp 24 30 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. for this example, the burst length = 4, and the cas latency = 2. 2. column-address a9 is a dont care on x8 version.
42 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram enable auto precharge t ch t cl t ck t ac t lz dqm clk a0-a9 dq ba a10 t oh d out m t ah t as t ah t as t ah t as row column m 2 row row row dont care undefined t oh d out m +3 t ac t oh t ac t oh t ac d out m +2 d out m +1 command t cmh t cms t cmh t cms nop nop active nop read nop active t oh d out t ac t ac read column b 2 enable auto precharge row active row bank 0 bank 0 bank 1 bank 1 bank 0 cke t ckh t cks t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 cas latency - bank 0 t rcd - bank 1 cas latency - bank 1 t t rc - bank 0 rrd t0 t1 t2 t3 t4 t5 t6 t7 t8 alternating bank read accesses 1 timing parameters -8b -10 symbol* min max min max units t ac(3) 6 7.5 ns t ac(2) 9 9 ns t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t lz 1 2 ns t oh 3 3 ns t ras 50 120,000 60 120,000 ns t rc 80 90 ns t rcd 20 30 ns t rp 24 30 ns t rrd 20 20 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. for this example, the burst length = 4, and the cas latency = 2. 2. column-address a9 is a dont care on x8 version.
43 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram read C full-page burst 1 t ch t cl t ck t ac t lz t rcd cas latency dqm cke clk a0-a9 dq ba oh d out m t ah t as t ac t oh d out m +1 row t hz t ac t oh d out m +1 t ac t oh d out m +2 t ac t oh d out m -1 t ac t oh d out m full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed. 1,024 (x4), 512 (x8) locations within the same row. dont care undefined command t cmh t cms t cmh t cms nop nop nop active nop read nop burst term nop nop ( ) ( ) ( ) ( ) nop column m 2 a10 t ah t as row ( ) ( ) ( ) ( ) t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) t0 t1 t2 t3 t4 t5 t6 tn + 1 tn + 2 tn + 3 tn + 4 3 timing parameters -8b -10 symbol* min max min max units t ac(3) 6 7.5 ns t ac(2) 9 9 ns t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t hz (3) 6 8 ns t hz (2) 7 10 ns t lz 1 2 ns t oh 3 3 ns t rcd 20 30 ns -8b -10 symbol* min max min max units *cas latency indicated in parentheses. note: 1. for this example, the cas latency = 2. 2. column-address a9 is a dont care on x8 version. 3. page left open; no t rp.
44 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram read C dqm operation 1 t ch t cl t ck t rcd cas latency dqm cke clk a0-a9 dq ba a10 row bank row bank dont care undefined t ac lz d out m t oh d out m +3 d out m +2 t t hz lz t command nop nop nop active nop read nop nop nop t hz t ac t oh t ac t oh t ah t as t cms t cmh t cms t cmh t ah t as t ah t as column m 2 t ckh t cks enable auto precharge disable auto precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -8b -10 symbol* min max min max units t ac(3) 6 7.5 ns t ac(2) 9 9 ns t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t hz (3) 6 8 ns t hz (2) 7 10 ns t lz 1 2 ns t oh 3 3 ns t rcd 20 30 ns -8b -10 symbol* min max min max units *cas latency indicated in parentheses. note: 1. for this example, the burst length = 4, and the cas latency = 2. 2. column-address a9 is a dont care on x8 version.
45 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram write C without auto precharge 1 disable auto precharge all banks t ch t cl t ck t rp t ras t rcd t rc dqm cke clk a0-a9 dq ba a10 t cmh t cms t ah t as row row bank bank bank row row bank t wr dont care undefined d in m t dh t ds d in m +1 d in m +2 d in m +3 command t cmh t cms nop nop nop active nop write nop precharge active t ah t as t ah t as t dh t ds t dh t ds t dh t ds single bank t ckh t cks column m 3 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t dh 1 1 ns t ds 2 3 ns t ras 50 120,000 60 120,000 ns t rc 80 90 ns t rcd 20 30 ns t rp 24 30 ns t wr [a1] 10 10 ns t wr [a2] 15 15 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. for this example, the burst length = 4, and the write burst is followed by a manual precharge with the a1 version. 2. 10ns (a1) or 15ns (a2) are required between and the precharge command, regardless of frequency. 3. column-address a9 is a dont care on x8 version.
46 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram write C with auto precharge 1 enable auto precharge t ch t cl t ck t rp t ras t rcd t rc dqm cke clk a0-a9 dq ba a10 t cmh t cms t ah t as row row bank bank row row bank t wr dont care undefined d in m t dh t ds d in m +1 d in m +2 d in m +3 command t cmh t cms nop nop nop active nop write nop active t ah t as t ah t as t dh t ds t dh t ds t dh t ds t ckh t cks nop nop column m 3 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t dh 1 1 ns t ds 2 3 ns t ras 50 120,000 60 120,000 ns t rc 80 90 ns t rcd 20 30 ns t rp 24 30 ns t wr [a1] 1 1 t ck t wr [a2] 2 2 t ck *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. for this example, the burst length = 4 with the a2 version, i.e., two-clock minimum for t wr. 2. the a1 version requires one clock between and the precharge command, provided t wr is met. 3. column-address a9 is a dont care on x8 version. 4. with auto precharge.
47 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram t ch t cl t ck clk dq t wr - bank 0 dont care undefined d in m t dh t ds d in m +1 d in m +2 d in m +3 command t cmh t cms nop nop active nop write nop active t dh t ds t dh t ds t dh t ds active write d in b t dh t ds d in b +1 d in b +2 t dh t ds t dh t ds enable auto precharge dqm a0-a9 ba a10 t cmh t cms t ah t as t ah t as t ah t as row row row row enable auto precharge row row bank 0 bank 0 bank 1 bank 0 bank 1 cke t ckh t cks column b 3 column m 3 2 t0 t1 t2 t3 t4 t5 t6 t7 t8 t rp - bank 0 t ras - bank 0 t rcd - bank 0 t rcd - bank 0 t rcd - bank 1 t t rc - bank 0 rrd alternating bank write accesses 1 timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t dh 1 1 ns t ds 2 3 ns t ras 50 120,000 60 120,000 ns t rc 80 90 ns t rcd 20 30 ns t rp 24 30 ns t rrd 20 20 ns t wr [a1] note 2 note 2 C t wr [a2] note 2 note 2 C *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. for this example, the burst length = 4 with the a2 version, i.e., one-clock minimum for t wr. 2. the a1 version requires one clock with auto precharge or 10ns with precharge between and the precharge command. the a2 version requires two clocks with auto precharge or 15ns with precharge. 3. column-address a9 is a dont care on x8 version.
48 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram write C full-page burst t ch t cl t ck t rcd dqm cke clk a0-a9 ba a10 t ah t as t ah t as row row full-page burst does not self-terminate. can use burst terminate command. ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) full page completed. dont care undefined command t cmh t cms t cmh t cms nop nop nop active nop write burst term nop nop ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) dq d in m t dh t ds d in m +1 d in m +2 d in m +3 t dh t ds t dh t ds t dh t ds d in m -1 t dh t ds t dh t ds column m 1 t ah t as bank ( ) ( ) ( ) ( ) bank t ckh t cks ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) 1,024 (x4), 512 (x8) locations within the same row. 2, 3 t0 t1 t2 t3 t4 t5 tn + 1 tn + 2 tn + 3 t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t dh 1 1 ns t ds 2 3 ns t rcd 20 30 ns timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. column-address a9 is a dont care on x8 version. 2. t wr must be satisfied prior to precharge command. 3. page left open, no t rp.
49 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram t ch t cl t ck t rcd dqm cke clk a0-a9 dq ba a10 t ah t as row bank row bank enable auto precharge d in m +3 t dh t ds d in m d in m +2 command nop nop nop active nop write nop nop dont care undefined t cms t cmh t cms t cmh t dh t ds t dh t ds t ah t as t ah t as disable auto precharge column m 2 t ckh t cks t0 t1 t2 t3 t4 t5 t6 t7 write C dqm operation 1 t cks 2 3 ns t cmh 1 1 ns t cms 2 3 ns t dh 1 1 ns t ds 2 3 ns t rcd 20 30 ns timing parameters -8b -10 symbol* min max min max units t ah 1 1 ns t as 2 3 ns t ch 3 3.5 ns t cl 3 3.5 ns t ck (3) 8 10 ns t ck (2) 12 15 ns t ckh 1 1 ns *cas latency indicated in parentheses. -8b -10 symbol* min max min max units note: 1. for this example, the burst length = 4. 2. column-address a9 is a dont care on x8 version.
50 16 meg: x4, x8 sdram micron technology, inc., reserves the right to change products or specifications without notice. 16msdramx4x8_b.p65 C rev. 5/98 ?1998, micron technology, inc. 16 meg: x4, x8 sdram 44-pin plastic tsop (400 mil) note: 1. all dimensions in inches (millimeters) max or typical where noted. min 2. package width and length do not include mold protrusion; allowable mold protrusion is .01" per side. .459 (11.66) .047 (1.2) max .004 (0.10) 1 .0315 (0.80) typ 22 .018 (0.45) .012 (0.30) .398 (10.11) .722 (18.34) 44 .0315 (0.80) detail a .002 (0.05) .0315 (0.80) .005 (0.13) see detail a .728 (18.49) .467 (11.86) .402 (10.21) .007 (0.18) .006 (0.20) .016 (0.40) .024 (0.60) .010 (0.25) gage plane pin #1 id typ 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 e-mail: prodmktg@micron.com, internet: http://www.micron.com, customer comment line: 800-932-4992 micron is a registered trademark and the micron logo and m logo are trademarks of micron technology, inc.

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